With the development of modern silicon technology, more and more high-frequency circuits can be implemented in standard CMOS process. Radio-frequency (RF) integrated circuits (IC) in standard CMOS technology have proven feasible. However, further integration of T/R antenna switches in CMOS is quite challenging due to the higher loss of silicon substrate and lower linearity of CMOS devices.
For years RF switch has been dominated by discrete components using p-type, intrinsic, n-type (PIN) diodes and III-V metal-semiconductor field-effect transistors (MESFETs). Recently, CMOS T/R switch design has been explored to a certain extent. In relation to insertion loss, publication “A 0.5-μm CMOS T/R Switch for 900-MHz Wireless Applications”, Huang F. J. et al, IEEE Journal of Solid-State Circuits, Vol. 36 No. 3, pp. 486-492, March 2001 and publication “5.8-GHz CMOS T/R Switches With High and Low Substrate Resistances in a 0.18-μm CMOS Process”, Li Z. B. et al, IEEE Microwave and Wireless Components Letters, Vol. 13, No. 1, pp. 1-3, January 2003 reported that low insertion loss can be achieved by optimizing the transistor widths and bias voltages, by minimizing the substrate resistances, and by dc biasing the transmit and receive nodes, which decreases the capacitances while increasing the power 1-dB compression point.
In relation to isolation, publication “A High-performance CMOS-SOI Antenna Switch for the 2.5-5-GHz’, Carlo Tinella et al, IEEE Journal of Solid-State Circuits, Vol. 38, No. 7, pp. 1279-1283, July 2003 reported that a high isolation can be achieved by taking advantage of the high resistive substrate and underlying oxide of silicon-on-insulator (SOI) technology. However, in these respective publications, linearity was limited due to parasitic capacitance and source-drain junction diodes. Thus various techniques are developed to achieve higher linearity.
One technique to increase linearity is the body floating technique. Publication “Integrated CMOS Transmit-Receive Switch Using LC_tuned Substrate Bias for 2.4-GHz and 5.2-GHz Applications”, Niranjan A. Talwalkar et al, IEEE Journal of Solid-State Circuits, Vol. 39, No. 6, pp. 863-870, June 2004 introduced a body floating technique involving an inductive substrate bias scheme. The bias scheme uses an inductor-capacitor (L/C) tank to enhance the linearity of the metal oxide semiconductor field-effect transistor (MOSFET) when used as a pass gate at RF. However, this technique has the disadvantages of design complexity and consumption of large silicon area.
Taking advantage of triple-well CMOS process, another body floating technique can be realized using a large resistor to bias the body or bulk as reported in publication “Design and Analysis for a Miniature CMOS SPDT Switch Using Body-Floating Technique to improve Power Performance”, Yeh M. C et al, IEEE Transactions on Microwave Theory and Techniques”, Vol. 54, No. 1, pp. 31-39, January 2006. As resistors are intrinsically wideband, the linearity improvement of this technique is also wideband.
Another technique to improve linearity involves the use of stacked transistors. Publication “21.5-dBm Power-Handling 5-GHz Transmit/Receive CMOS Switch Realized by Voltage Division Effect of Stacked Transistor Configuration With Depletion-Layer-Extended Transistors (DETs), Takahiro Ohnakado et al, IEEE Journal of Solid-State Circuits, Vol. 39, No. 4, pp. 577-584, April 2004 reported a T/R CMOS switch utilizing the depletion-layer-extended transistor (DET), which possesses high effective substrate resistance and enables the voltage division effect of the stacked transistor configuration to work in the CMOS switch. Although linearity is improved, insertion loss will be degraded and has to be compensated by the DET.
Yet another technique to improve linearity involves integration of on-chip LC impedance transformation networks (ITNs) into a switch. Publication “15-GHz Fully Integrated nMOS Switches in a 0.13-μm CMOS Process” reported two fully integrated nMOS switches which have been demonstrated at 15 GHz in a 0.13-m CMOS foundry process. One switch incorporates on-chip LC ITNs while the second switch does not. The switches with and without ITNs achieve the same 1.8-dB insertion loss at 15 GHz, but 21.5 and 15 dBm input P1dB, respectively. The degradation of insertion loss due to use of ITNs is compensated by reducing the mismatch loss caused by the bond pad parasitics. The switch without ITNs is suitable for 3.1-10.6 GHz ultra-wide-band (UWB) applications. The switch with ITNs has 5 dB worse isolation than the switch without. The difference is due to the larger transistor size of the switch with ITNs, which introduces lower parasitic impedance path between Tx/Rx ports and antenna port. In this publication, although linearity is improved, isolation performance is degraded.
Yet another technique to improve linearity involves the use of differential architectures. Publication “A Differential CMOS T/R Switch for Multistandard Applications”, Zhang Y. P. et al, IEEE Transactions on Circuits and Systems-II: Express Briefs, Vol. 53, No. 8, pp. 782-786, August 2006 presented a differential T/R switch integrated in a 0.18-m standard CMOS technology for wireless applications up to 6 GHz. This switch design employs a fully differential architecture to accommodate the design challenge of differential transceivers and improve the linearity performance. It exhibits less than 2-dB insertion loss, higher than 15-dB isolation, in a 60 m×40 m area. 15-dBm power at 1-dB compression point (1 dB) is achieved without using additional techniques to enhance the linearity. This switch is suitable for differential transceiver front-ends with a moderate power level.
Comparing to other RF IC circuits that have been pushed up to 60-GHz, the current design of CMOS T/R switches for higher frequency operations are explored only to a limited extent. Most of these switches adopt series-shunt architecture. At higher frequencies, the loss due to the shunt arm will severely degrades the insertion loss, while the lack of shunt arm will result in low isolation. Therefore, an objective of the present invention is to provide an alternative T/R switch design with low insertion loss, high isolation, high linearity and high power handling capability thereby advantageously avoids or reduces some of the above-mentioned drawbacks of prior art devices.